為驗(yàn)證上文對(duì)電路中增益提高電路和共模反饋電路設(shè)計(jì)的正確性,采用Chartered 0.18um 1.8V CMOS工藝庫(kù),在Cadence 軟件仿真環(huán)境下進(jìn)行電路仿真.\x05
To test the circuit in the above paragraphs gain improve circuit and common-mode feedback circuit design is correct,the Chartered 0.18 um 1.8 V CMOS technology library,in Cadence software simulation environment circuit simulation.\x05
首先對(duì)2個(gè)增益提高進(jìn)行了仿真,是否滿(mǎn)足設(shè)計(jì)的要求.\x05
The first of two gain improve simulation,whether meet the design requirements.\x05
圖7,8是增益提高的頻率特性,信號(hào)通路上的N型增益提升電路的負(fù)載電容為1pF,從圖7中可以看出,其開(kāi)環(huán)直流增益為24dB,單位增益帶寬為1.44GHz,相位裕度為79°,P型增益提升電路的負(fù)載電容為0.6pF,從圖8中的頻率特性可以看出,其開(kāi)環(huán)直流增益為28dB,單位增益帶寬為1.39GHz,相位裕度為76°,滿(mǎn)足設(shè)計(jì)要求.\x05
Figure 7,8 is the gain improve frequency characteristics,signal path of ascension of n-type gain circuit load capacitance for 1 pF,can see from figure 7,the open loop dc gain for 24 dB,1.44 GHz bandwidth units gain,phase margin for 79 °,P type gain of the circuit for ascension load capacitance 0.6 pF,from the figure 8 can be seen in the frequency characteristics,the open loop dc gain for 28 dB,1.39 GHz bandwidth units gain,phase margin for 76 °,meet the design requirements.