VHDL程序
那位幫忙看下我這個程序哪里錯了呀,編譯的時候,說Error (10517): VHDL type mismatch error at /315jizhi.vhd(9): std_logic_vector type does not match integer literal
功能是實現(xiàn)316進制計數(shù)
程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt315 IS
PORT(clk , clrn : IN STD_LOGIC;
q : out std_logic);
END cnt315;
ARCHITECTURE one OF cnt315 IS
SIGNAL q1 : STD_LOGIC_vector RANGE 0 TO 3;
SIGNAL q2 : BIT_vector RANGE 0 TO 3;
SIGNAL q3 : BIT_vector RANGE 0 TO 3;
BEGIN
PROCESS(clk,clrn)
variable cnt : integer range 0 to 315;
begin
if(clrn = '1') then q1