急：vhdl語言編的移位寄存器編譯出現(xiàn)錯(cuò)誤
程序如下：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cpu_lib.all;
entity shift is
port ( a :in bit16; sel :in t_shift ; y :out bit16);
end shift;
architecture rtl of shift is
begin
shftproc:process(a,sel)
begin
case sel is
when shftpass =>y y y y y y