英語翻譯
VBMAR router adopts a concurrent architecture.Any physical channel except the one connecting to local processor is shared by two virtual channels.Each virtual channel is implemented as a data bus inside the router.So two data buses serve one physical channel.A control pipeline is set for each physical channel,which controls the moving of a message through the router.Thus multiple messages can be routed simultaneously.A control pipeline includes three stages,input control logic,routing control logic,and output control logic.Each stage drains a clock cycle.Message moves in the router stage by stage under control.A data bus is actually a data pipeline.A message spends 3 clock cycles to go through a router when no blocking exists.This concurrent architecture can improve the network throughput greatly than the commonly used single control logic architecture.
求不復制百度和google的翻譯，真心求大神翻譯！