能幫我看下 這個Type integer does not match with a string literal是怎么回事么、謝謝啦
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY vv IS
END vv;
ARCHITECTURE behavior OF vv IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comp
PORT(
a :IN integer range 0 to 7;
b :IN integer range 0 to 7;
sel :IN std_logic;
x1 :OUT std_logic;
x2 :OUT std_logic;
x3 :OUT std_logic
);
END COMPONENT;
--Inputs
signal a :integer range 0 to 7 :="00000010" ;
signal b :integer range 0 to 7 := "00000100";
signal sel :std_logic := '0';
\x05--Outputs
signal x1 :std_logic;
signal x2 :std_logic;
signal x3 :std_logic;
-- No clocks detected in port list.Replace below with
-- appropriate port name
BEGIN
\x05-- Instantiate the Unit Under Test (UUT)
uut:comp PORT MAP (
a => a,
b => b,
sel => sel,
x1 => x1,
x2 => x2,
x3 => x3
);
END;